----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:30:47 06/02/2010 
-- Design Name: 
-- Module Name:    Samples_to_Ram - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Samples_to_Ram is
    Port ( Data_A_in : in  STD_LOGIC_VECTOR (11 downto 0);
           Data_B_in : in  STD_LOGIC_VECTOR (11 downto 0);
           newdata_in : in  STD_LOGIC;
           Trigger_in : in  STD_LOGIC;
           Run_in : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           adr_out : out  STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
           data_out : out  STD_LOGIC_VECTOR (31 downto 0);
           we : out  STD_LOGIC := '0';
           ena : out  STD_LOGIC := '0';
			  clk_out : out STD_LOGIC := '0';
			  n_samples : in STD_LOGIC_VECTOR (11 downto 0);
			  n_presamples : in STD_LOGIC_VECTOR (11 downto 0);
			  trigger_out : out STD_LOGIC);
end Samples_to_Ram;

architecture Behavioral of Samples_to_Ram is
signal counter : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal adr_counter : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal data_a1 : STD_LOGIC_VECTOR (31 downto 0);
signal data_a2 : STD_LOGIC_VECTOR (31 downto 0);
signal data_b1 : STD_LOGIC_VECTOR (31 downto 0);
signal data_b2 : STD_LOGIC_VECTOR (31 downto 0);
signal trigger_flag :STD_LOGIC := '0';
signal done_flag :STD_LOGIC := '0';
signal Run_old :STD_LOGIC := '0';
signal adr_trigger : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal trigger_counter : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal offset_a : STD_LOGIC_VECTOR (11 downto 0) := "000001100000";
signal offset_b : STD_LOGIC_VECTOR (11 downto 0) := "100000110000";
signal newdata_inPos : STD_LOGIC := '0';

begin
P1: process(newdata_in, reset)
begin
	clk_out <= newdata_in;
	if reset = '1' then 
				done_flag <= '0';
				trigger_flag <= '0';
				trigger_counter <= "000000000000";
				adr_counter <= "000000000000";
				counter <= "00";
				data_a1 <= "00000000000000000000000000000000";
				data_a2 <= "00000000000000000000000000000000";
				data_b1 <= "00000000000000000000000000000000";
				data_b2 <= "00000000000000000000000000000000";
	elsif newdata_in='1' and newdata_inPos='0' then --rising edge
		if((Run_in = '1') and (done_flag = '0'))then
			if(counter = 0)then 
								data_a1(15 downto 0) 	<= Data_A_in & "0000";
								data_b1(15 downto 0) 	<= Data_B_in & "0000";
								data_out <= data_b2;
								adr_out <= adr_counter + offset_b;
								if(Run_old = '1') then adr_counter <= adr_counter + 1; end if;
			elsif(counter = 1)then
								data_a1(31 downto 16)	<= Data_A_in & "0000";
								data_b1(31 downto 16)	<= Data_B_in & "0000";
								data_out <= data_a1;
								adr_out <= adr_counter + offset_a;
			elsif(counter = 2)then 
								data_a2(15 downto 0) 	<= Data_A_in & "0000";
								data_b2(15 downto 0) 	<= Data_B_in & "0000";
								data_out <= data_b1;
								adr_out <= adr_counter + offset_b;
								adr_counter <= adr_counter + 1;
			elsif(counter = 3)then
								data_a2(31 downto 16)	<= Data_A_in & "0000";
								data_b2(31 downto 16)	<= Data_B_in & "0000";	
								data_out <= data_a2;
								adr_out <= adr_counter + offset_a;
			end if;
			
			if(Trigger_in = '1') then 
					trigger_flag <= '1';
					adr_trigger <= adr_counter;
					trigger_counter <= "000000000000";
			elsif ((trigger_flag = '1') and (done_flag = '0') and ((counter = 0) or (counter = 2)) )then
						trigger_counter <= trigger_counter + 1;
			end if;
			
					
			
			counter <= counter + 1;
			
			
			if(counter > 3) then counter <= "00"; end if;
			if(adr_counter >= 2000) then adr_counter <= "000000000000"; end if; -- 2000 * 2 Values = 4000
			if(trigger_counter >= (n_samples - n_presamples)) then 
				done_flag <= '1'; 
				trigger_out <= '1';
				adr_out <= "000000011110";
				data_out <= "00000000000000000000" & adr_trigger;
			else
				trigger_out <= '0';
			end if;
			
			if(Run_old = '1') then
			we <= '1';
			ena <= '1';
			end if;
			Run_old <= Run_in;	
			
		elsif((Run_in = '0') and (done_flag = '1'))then 
				done_flag <= '0';
				trigger_flag <= '0';
				trigger_counter <= "000000000000";
				adr_counter <= "000000000000";
				counter <= "00";
				data_a1 <= "00000000000000000000000000000000";
				data_a2 <= "00000000000000000000000000000000";
				data_b1 <= "00000000000000000000000000000000";
				data_b2 <= "00000000000000000000000000000000";
			
	end if;
	end if;
	newdata_inPos <= newdata_in;
end process;
end Behavioral;

